In fabrication of semiconductor devices on a wafer, measurements of current leakage of dielectric sections of the device are an important part of the overall process, to check that the sections formed conform to their nominal specifications. Leakage measurements are particularly important for dielectric layers, such as those used in dynamic random access memory (DRAM) capacitors, and those forming the gates of transistors. At present, leakage measurements are typically performed on relatively large test structures having sizes greater than 50 μm×50 μm, the test structures being located at a periphery of a die. The test structures simulate the conditions of the layer or section being tested. Measurements of such test structures require that physical connections be made to the structure, so that currents through the structure can be measured.
A method for measuring properties of wafer components using three non-contact techniques is described in an article titled “Diagnosing Processing Problems through Electrical Charge Characterization” by Horner et al., in the Autumn 1999 edition of Yield Management Solutions. The article may be found at www.kla-tencor.com/company/magazine/autumn99.html, and is incorporated herein by reference. To perform a measurement, a corona discharge biases the surface of a wafer being inspected, and a vibrating Kelvin probe monitors the wafer surface potential as a function of the charge. A pulsed light source linked to the Kelvin probe is used to generate a photo-voltage. The authors state that use of the three techniques allows extraction of electrical properties of a system being inspected.
A number of other methods for measuring wafer parameters are known in the art. Some of these methods use an electron beam having a variable energy so as to cover both positive and negative charging domains of the materials irradiated by the beam. The positive charging domain is the range of electron energies in which the total yield of secondary and backscattered electrons from the surface layer is greater than the primary electron beam current, while the negative charging domain is the range in which the total yield is less than the primary beam current. These domains are described, for example, by Yacobi et al., in Microanalysis of Solids (Plenum Press, New York, 1994) on pages 38–39.
U.S. Patent Application Publication 2003/0071646 to Neo et al., whose disclosure is incorporated herein by reference, describes a method for evaluating a pn junction. The junction is reverse biased, irradiated with an electron beam, and secondary electrons from the junction are collected. The operation is performed sequentially, and a relaxation time of the junction may be determined from the image formed by the secondary electrons.
U.S. Pat. No. 6,294,918 to Hung, whose disclosure is incorporated herein by reference, describes a method for locating a weak circuit in an integrated circuit (IC). An electron beam scans the surface of the IC to determine a threshold current that causes failure in a circuit of the IC. A functionality tester functions simultaneously with the electron beam, and is used to locate weak circuits having insufficient driving currents.
U.S. Pat. No. 6,504,393 to Lo et al., whose disclosure is incorporated herein by reference, describes apparatus for testing a semiconductor structure. The apparatus includes a system, which may be an electron beam, for charging the structure, and an electric field generator which applies a field perpendicular to the surface of the structure to determine the potential of the charge. The charged structure is interrogated with a charged particle beam, such as the electron beam. A secondary electron detector in the apparatus is used to determine voltage contrast data for the structure.
U.S. Pat. No. 6,700,122 to Matsui et al., whose disclosure is incorporated herein by reference, describes a technique for detecting defects in a wafer. An electron beam scans the wafer while the wafer is being moved, and secondary electrons generate an image of the wafer surface. The image may be analyzed to find both the type and the position of defects.
U.S. Pat. No. 6,753,194 to Ushiki et al., whose disclosure is incorporated herein by reference, describes irradiating a region of a semiconductor wafer with an electron beam in order to determine contaminants of the region. A current flowing from the region is measured, and a degree of contamination of the region is determined in response to the current.
An article titled “Reliability limits for the gate insulator in CMOS technology” by Stathis, in the IBM Journal of Research and Development 46, Numbers 2/3, 2002, is incorporated herein by reference. The article describes properties of gates of transistors; inter alia, the article states that for a SiO2 gate thickness of ˜1.5 nm, a current density greater than about 10 A/cm2 is viewed as leakage.